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[AVR] Implement disassembly support for I/O instructions
authorAyke van Laethem <aykevanlaethem@gmail.com>
Wed, 5 Feb 2020 14:04:47 +0000 (15:04 +0100)
committerAyke van Laethem <aykevanlaethem@gmail.com>
Wed, 10 Jun 2020 18:55:47 +0000 (20:55 +0200)
commit1ba7809793913daae4e15d8ca6acbf80db21816d
treefab6296262ffc31f7a1cdd7370012d784b307d11tree | snapshot
parent6e1eee6034f7220f170cb78b8a1334cff2b8b911commit | diff
[AVR] Implement disassembly support for I/O instructions

The in, out, and sbi/cbi family of instructions seem to require a custom
decoder. I'm not exactly sure why and would prefer to convince TableGen
to provide the correct decoders for these, but I can't seem to convince
it to do so. They simply disassemble without any operands.

Differential Revision: https://reviews.llvm.org/D74049
llvm/lib/Target/AVR/AVRInstrFormats.td diff | blob | history
llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp diff | blob | history
llvm/test/MC/AVR/inst-cbi.s diff | blob | history
llvm/test/MC/AVR/inst-in.s diff | blob | history
llvm/test/MC/AVR/inst-out.s diff | blob | history
llvm/test/MC/AVR/inst-sbi.s diff | blob | history
llvm/test/MC/AVR/inst-sbic.s diff | blob | history
llvm/test/MC/AVR/inst-sbis.s diff | blob | history
Domain: System / Toolchain;