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(parent: 3b5c734) | patch
clk: renesas: r9a07g044: Add clock and reset entries for ADC
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 19 Jul 2021 08:58:39 +0000 (09:58 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 19 Jul 2021 09:22:23 +0000 (11:22 +0200)
commit1b87d5bba32c1f25a12ba0625546e5375e3f998d
tree95c3270e2432b8bdeaabf360b1633b2241e534bftree | snapshot
parent3b5c734592ade51fed3982bc840a830e066e668ecommit | diff
clk: renesas: r9a07g044: Add clock and reset entries for ADC

Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719085840.21842-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
Domain: System / Kernel;