drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout
authorImre Deak <imre.deak@intel.com>
Mon, 9 Apr 2018 12:27:16 +0000 (15:27 +0300)
committerImre Deak <imre.deak@intel.com>
Tue, 10 Apr 2018 10:12:22 +0000 (13:12 +0300)
commit1b85147b4b8fb90da51b6e94a3e6c30469bf1de1
tree240e780acddfc016f55dddc56281a17daa9ccb4d
parent8b69449d26637551c4145731e684cf1bb2478393
drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks
like they happen sometime after a system suspend/resume cycle, with the
same power well enabling succeeding both before and after the failed
one and no other problems observed. The current timeout in the code is
not actually specified by BSpec, so let's try to increase that until a
BSpec update.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180409122716.4055-1-imre.deak@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
drivers/gpu/drm/i915/intel_dpio_phy.c