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AMDGPU/GlobalISel: Select G_SHL
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 16 Jul 2019 20:15:30 +0000 (20:15 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 16 Jul 2019 20:15:30 +0000 (20:15 +0000)
commit1b69fd275d589f48ce63bea73e311b7ef89c99ba
treebb2775b59c9c64710bb7ed48d30b21267c807a61tree | snapshot
parentb157dcacb5b96fd64900906911832a8ac3bb189ecommit | diff
AMDGPU/GlobalISel: Select G_SHL

I think this manages to not break the DAG handling with the divergent
predicates because the stadalone divergent patterns end up with a
higher priority than the pattern on the instruction definition.

The 16-bit versions don't work yet.

llvm-svn: 366254
llvm/lib/Target/AMDGPU/SOPInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/VOP2Instructions.td diff | blob | history
llvm/lib/Target/AMDGPU/VOP3Instructions.td diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir [new file with mode: 0644] blob
Domain: System / Toolchain;