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(parent: a5ab04a) | patch
clk: at91: sama7g5: fix parents of PDMCs' GCLK
authorCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
Fri, 4 Mar 2022 18:26:16 +0000 (20:26 +0200)
committerNicolas Ferre <nicolas.ferre@microchip.com>
Tue, 8 Mar 2022 14:35:35 +0000 (15:35 +0100)
commit1a944729d8635fa59638f24e8727d5ccaa0c8c19
tree69000ad631b27030be93d0e1eaccfa733f6d6a81tree | snapshot
parenta5ab04af49434aef532bf6cd4baa08a13665d608commit | diff
clk: at91: sama7g5: fix parents of PDMCs' GCLK

Audio PLL can be used as parent by the GCLKs of PDMCs.

Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
drivers/clk/at91/sama7g5.c diff | blob | history
Domain: System / Kernel;