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armv8: fsl-layerscape: Update ddr erratum a008336
authorShengzhou Liu <Shengzhou.Liu@nxp.com>
Fri, 26 Aug 2016 10:30:38 +0000 (18:30 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 14 Sep 2016 21:05:20 +0000 (14:05 -0700)
commit1a87c24fe8f4c8afc735aa50b8fc9eaa2f230c0f
tree3977d2c8cae7f96374254e30a4125409fcb256fdtree | snapshot
parent77b571da3b2c2fd46d6a80e4e045f3aae392d979commit | diff
armv8: fsl-layerscape: Update ddr erratum a008336

DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/soc.c diff | blob | history
Domain: System / Kernel;