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(parent: de22455) | patch
clk: tegra: fix SS control on PLL enable/disable
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Tue, 25 Jul 2017 10:34:02 +0000 (13:34 +0300)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 23 Aug 2017 22:56:53 +0000 (15:56 -0700)
commit1a7da87727acfc201141d67e6edf2fb4ddcab7db
treed7bff74b07e86abef51429c4e8092495cc8681d7tree | snapshot
parentde2245540ed84c56ba3d71d1ce8e14fdaf332720commit | diff
clk: tegra: fix SS control on PLL enable/disable

PLL SS was only controlled when setting the PLL rate, not when the PLL itself
is enabled or disabled.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/tegra/clk-pll.c diff | blob | history
Domain: System / Kernel;