[PowerPC] Inefficient register allocation of ACC registers results in many copies.
authorStefan Pintilie <stefanp@ca.ibm.com>
Mon, 12 Jul 2021 17:47:44 +0000 (12:47 -0500)
committerStefan Pintilie <stefanp@ca.ibm.com>
Tue, 20 Jul 2021 15:53:40 +0000 (10:53 -0500)
commit1a6dc92be7d68611077f0fb0b723b361817c950c
treea031b51e94fedc24292ee85df21141a616d58624
parentbbbc4f110e35ac709b943efaa1c4c99ec073da30
[PowerPC] Inefficient register allocation of ACC registers results in many copies.

ACC registers are a combination of four consecutive vector registers.
If the vector registers are assigned first this often forces a number
of copies to appear just before the ACC register is created. If the ACC
register is assigned first then fewer copies are generated when the vector
registers are assigned.

This patch tries to force the register allocator to assign the ACC registers first
and then the UACC registers and then the vector pair registers. It does this
by changing the priority of the register classes.

This patch also adds hints to help the register allocator assign UACC registers from
known ACC registers and vector pair registers from known UACC registers.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D105854
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll