[SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.
authorCraig Topper <craig.topper@sifive.com>
Sun, 21 Feb 2021 19:13:34 +0000 (11:13 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sun, 21 Feb 2021 19:13:36 +0000 (11:13 -0800)
commit1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144
tree95bc5f5a533f207925504b5cc305ea5f0c1bc35f
parentbae04a3e2d69d474e47ce1a23109efa0036e8cf7
[SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.

This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.

Reviewed By: luismarques, RKSimon

Differential Revision: https://reviews.llvm.org/D97133
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoM.td
llvm/test/CodeGen/Mips/llvm-ir/srem.ll
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll