drm/i915/dsi: fix DSS CTL register offsets for TGL+
authorJani Nikula <jani.nikula@intel.com>
Wed, 1 Mar 2023 15:14:09 +0000 (17:14 +0200)
committerJani Nikula <jani.nikula@intel.com>
Mon, 6 Mar 2023 12:32:07 +0000 (14:32 +0200)
commit1a62dd9895dca78bee28bba3a36f08836fdd143d
tree4f145b38d13dbd60cafa459e173c4b30173d45e4
parent12e8ed969852c11503216115952c84f7c2f4c6b5
drm/i915/dsi: fix DSS CTL register offsets for TGL+

On TGL+ the DSS control registers are at different offsets, and there's
one per pipe. Fix the offsets to fix dual link DSI for TGL+.

There would be helpers for this in the DSC code, but just do the quick
fix now for DSI. Long term, we should probably move all the DSS handling
into intel_vdsc.c, so exporting the helpers seems counter-productive.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230301151409.1581574-1-jani.nikula@intel.com
drivers/gpu/drm/i915/display/icl_dsi.c