[InstCombine] fold mask-with-signbit-splat to icmp+select
authorSanjay Patel <spatel@rotateright.com>
Tue, 14 Dec 2021 20:18:10 +0000 (15:18 -0500)
committerSanjay Patel <spatel@rotateright.com>
Tue, 14 Dec 2021 21:00:42 +0000 (16:00 -0500)
commit1a60ae02c65d26981017f59bc5918d3c2e363bfd
treeb49161c553cdb13ac710858db0f48c34b682887d
parent96130b5dc7f600e0c8f5e850ddddfaba952bba34
[InstCombine] fold mask-with-signbit-splat to icmp+select

~(iN X s>> (N-1)) & Y --> (X s< 0) ? 0 : Y

https://alive2.llvm.org/ce/z/JKlQ9x

This is similar to D111410 / 727e642e970d028049d ,
but it includes a 'not' of the signbit and so it
saves an instruction in the basic pattern.

DAGCombiner or target-specific folds can expand
this back into bit-hacks.

The diffs in the logical-select tests are not true
regressions - running early-cse and another round
of instcombine is expected in a normal opt pipeline,
and that reduces back to a minimal form as shown
in the duplicated PhaseOrdering test.

I have no understanding of the SystemZ diffs, so
I made the minimal edits suggested by FileCheck to
make that test pass again. That whole test file is
wrong though. It is running the entire optimizer (-O2)
to check IR, and then topping that by even running
codegen and checking asm. It needs to be split up.

Fixes #52631
clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
llvm/test/Transforms/InstCombine/and.ll
llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll
llvm/test/Transforms/InstCombine/logical-select.ll
llvm/test/Transforms/InstCombine/vec_sext.ll
llvm/test/Transforms/PhaseOrdering/vector-select.ll