[MIR] Add comments to INLINEASM immediate flag MachineOperands
authorKonstantin Schwarz <konstantin.schwarz@hightec-rt.com>
Tue, 14 Apr 2020 07:24:40 +0000 (09:24 +0200)
committerKonstantin Schwarz <konstantin.schwarz@hightec-rt.com>
Thu, 16 Apr 2020 11:46:14 +0000 (13:46 +0200)
commit1a3e89aa2bd26ad05b25635457bad28f46427eeb
tree47d38fd357eafecb108495e69f6aba5bb2d87436
parent43e2460a89abf6aace35973c682e1723d5f16f10
[MIR] Add comments to INLINEASM immediate flag MachineOperands

Summary:
The INLINEASM MIR instructions use immediate operands to encode the values of some operands.
The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature.

Reviewers: SjoerdMeijer, arsenm, efriedma

Reviewed By: arsenm

Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78088
28 files changed:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/include/llvm/IR/InlineAsm.h
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/test/CodeGen/AArch64/seqpairspill.mir
llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
llvm/test/CodeGen/Thumb2/high-reg-spill.mir
llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
llvm/test/CodeGen/X86/stack-folding-adx.mir
llvm/test/CodeGen/X86/stack-folding-bmi2.mir
llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir