i915/display/dp: SDP CRC16 for 128b132b link layer
authorArun R Murthy <arun.r.murthy@intel.com>
Thu, 2 Mar 2023 08:15:32 +0000 (13:45 +0530)
committerJani Nikula <jani.nikula@intel.com>
Tue, 21 Mar 2023 14:17:20 +0000 (16:17 +0200)
commit1a324a40b452ae0a57676369c0a0150674728853
treeb8120a8c3e4d55b25dc2334fbe124bbaa48f9aa1
parent562334d22a05a4793a620a9ef02516f3b8da9ec5
i915/display/dp: SDP CRC16 for 128b132b link layer

Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.

v2: Moved the CRC enable to link training init(Jani N)
v3: Moved crc enable to ddi pre enable <Jani N>
v4: Separate function for SDP CRC16 (Jani N)

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230302081532.765821-3-arun.r.murthy@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_dp_link_training.c
drivers/gpu/drm/i915/display/intel_dp_link_training.h