[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Tue, 31 Jan 2023 19:12:45 +0000 (20:12 +0100)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Wed, 8 Feb 2023 06:57:27 +0000 (07:57 +0100)
commit19a59099095b3cbc9846e5330de26fca0a44ccbe
tree51e6b45b3c78fa4eef9cb4176ef0d3f7110195a7
parent656188ddc4075eb50260607b3497589873f373d2
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Differential Revision: https://reviews.llvm.org/D143439
16 files changed:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c [new file with mode: 0644]
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c [new file with mode: 0644]
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
llvm/test/CodeGen/RISCV/imm.ll
llvm/test/CodeGen/RISCV/rotl-rotr.ll
llvm/test/CodeGen/RISCV/rv32xtheadbb.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll [new file with mode: 0644]