[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants
authorDavid Sherwood <david.sherwood@arm.com>
Mon, 22 Nov 2021 11:38:06 +0000 (11:38 +0000)
committerDavid Sherwood <david.sherwood@arm.com>
Mon, 17 Jan 2022 11:08:57 +0000 (11:08 +0000)
commit197f3c0deb76951315118ef13937b67ea9cbd5aa
tree5c39e3f09935dbe40d8fec7d6fb9c6c2663eb6b7
parent5f2edada68716190b3d62e60fd097c6101a1a1d4
[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants

When we know the value we're extending is a negative constant then it
makes sense to use SIGN_EXTEND because this may improve code quality in
some cases, particularly when doing a constant splat of an unpacked vector
type. For example, for SVE when splatting the value -1 into all elements
of a vector of type <vscale x 2 x i32> the element type will get promoted
from i32 -> i64. In this case we want the splat value to sign-extend from
(i32 -1) -> (i64 -1), whereas currently it zero-extends from
(i32 -1) -> (i64 0xFFFFFFFF). Sign-extending the constant means we can use
a single mov immediate instruction.

New tests added here:

  CodeGen/AArch64/sve-vector-splat.ll

I believe we see some code quality improvements in these existing
tests too:

  CodeGen/AArch64/reduce-and.ll
  CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll

The apparent regressions in CodeGen/AArch64/fast-isel-cmp-vec.ll only
occur because the test disables codegen prepare and branch folding.

Differential Revision: https://reviews.llvm.org/D114357
14 files changed:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/test/CodeGen/AArch64/funnel-shift.ll
llvm/test/CodeGen/AArch64/reduce-and.ll
llvm/test/CodeGen/AArch64/sve-vector-splat.ll
llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll