soc/tegra: pmc: Fix imbalanced clock disabling in error code path
authorDmitry Osipenko <digetx@gmail.com>
Tue, 2 Mar 2021 12:24:58 +0000 (15:24 +0300)
committerThierry Reding <treding@nvidia.com>
Fri, 26 Mar 2021 12:10:25 +0000 (13:10 +0100)
commit19221e3083020bd9537624caa0ee0145ed92ba36
tree685db67661ad55cdabfbe0f19c2e23f852001920
parentef85bb582c41524e9e68dfdbde48e519dac4ab3d
soc/tegra: pmc: Fix imbalanced clock disabling in error code path

The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/soc/tegra/pmc.c