R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
authorMarek Olsak <marek.olsak@amd.com>
Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)
committerMarek Olsak <marek.olsak@amd.com>
Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)
commit191507e0b730e95321d2b4126e8a0220e013bdcd
treeffe61d5f7391b694de65af81a160a844cc7be19d
parent7585a29bd426bdcfc90e6cbc64abb871273ca389
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI

This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 227990
llvm/lib/Target/R600/SIInstrInfo.cpp
llvm/lib/Target/R600/SIInstrInfo.td
llvm/lib/Target/R600/SIInstructions.td
llvm/test/CodeGen/R600/shl.ll
llvm/test/CodeGen/R600/sra.ll