[ARM] Fix vcvtb/t.f16 input liveness
authorDavid Green <david.green@arm.com>
Wed, 25 May 2022 11:16:26 +0000 (12:16 +0100)
committerDavid Green <david.green@arm.com>
Wed, 25 May 2022 11:16:26 +0000 (12:16 +0100)
commit18cb3b35066e5f385fa08d373c60447a3aa88ce3
tree237508a2aea2afde07723410c6b41f4ccff4ec91
parent730dc4e9bce8189c037a32e520d18b141250d265
[ARM] Fix vcvtb/t.f16 input liveness

The `vcvtb.f16.f32 Sd, Sn` (and vcvtt.f16.f32) instruction convert a f32
into a f16, writing either the top or bottom halves of the register.
That means that half of the input register Sd is used in the output.
This wasn't being modelled in the instructions, leading later analyses
to believe that the registers were dead where they were not, generating
invalid scheduling

Fix that be specifying the input Sda register for the instructions too,
allowing them to be set for cases like vector inserts. Most of the
changes are plumbing through the constraint string, cstr.

Differential Revision: https://reviews.llvm.org/D126118
llvm/lib/Target/ARM/ARMInstrFormats.td
llvm/lib/Target/ARM/ARMInstrVFP.td
llvm/test/CodeGen/ARM/aes-erratum-fix.ll
llvm/test/CodeGen/Thumb2/mve-div-expand.ll
llvm/test/CodeGen/Thumb2/mve-fmath.ll
llvm/test/CodeGen/Thumb2/mve-masked-store.ll
llvm/test/CodeGen/Thumb2/mve-vcvt.ll
llvm/test/CodeGen/Thumb2/mve-vcvt16.ll