AMDGPU/GlobalISel: Legalize odd sized loads with widening
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 26 Jun 2020 23:02:46 +0000 (19:02 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 20 Aug 2020 20:15:53 +0000 (16:15 -0400)
commit18b218007db69627bb651bb2a548afe92d615cd3
treef42373472d45260f9e50ce8a7142037a54831d07
parent54d8ded4b19aeba05006367766d148d34be01c02
AMDGPU/GlobalISel: Legalize odd sized loads with widening

Custom lower and widen odd sized loads up to the alignment. The
default set of legalization actions doesn't have a way to represent
this. This fixes naturally aligned <3 x s8> and <3 x s16> loads.

This also starts moving towards eliminating the buggy and
overcomplicated legalization rules for narrowing. All the memory size
changes should be done in the lower or custom action, not NarrowScalar
/ FewerElements. These currently have redundant and ambiguous code
with the lower action.
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir