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(parent: e36f014) | patch
clk: tegra: SDMMC controllers are on APB
authorAndrew Bresticker <abrestic@chromium.org>
Thu, 6 Nov 2014 22:47:55 +0000 (14:47 -0800)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Mon, 2 Feb 2015 13:46:14 +0000 (15:46 +0200)
commit18abd16376ad88ed3995c63ddae47be78bd56abe
tree149e4b0e10e149d65d4cef3f0f9a0c6f76a17394tree | snapshot
parente36f014edff70fc02b3d3d79cead1d58f289332ecommit | diff
clk: tegra: SDMMC controllers are on APB

Since the SDMMC controller registers are accessed via the APB,
the APB must be flushed before gating the SDMMC clocks to prevent
register accesses to the SDMMC controllers after their clocks are
gated.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
drivers/clk/tegra/clk-tegra-periph.c diff | blob | history
Domain: System / Kernel;