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RISC-V: Clear load reservations while restoring hart contexts
authorPalmer Dabbelt <palmer@sifive.com>
Wed, 25 Sep 2019 00:15:56 +0000 (17:15 -0700)
committerPaul Walmsley <paul.walmsley@sifive.com>
Tue, 1 Oct 2019 20:16:40 +0000 (13:16 -0700)
commit18856604b3e7090ce42d533995173ee70c24b1c9
tree2d52b920be2bb0dc54bb4ad0dd88413a7be5fceetree | snapshot
parent54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5ccommit | diff
RISC-V: Clear load reservations while restoring hart contexts

This is almost entirely a comment.  The bug is unlikely to manifest on
existing hardware because there is a timeout on load reservations, but
manifests on QEMU because there is no timeout.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
arch/riscv/include/asm/asm.h diff | blob | history
arch/riscv/kernel/entry.S diff | blob | history
Domain: System / Kernel;