drm/i915/icl: add the main CDCLK functions
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Tue, 6 Feb 2018 19:33:46 +0000 (17:33 -0200)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Tue, 13 Feb 2018 12:16:04 +0000 (10:16 -0200)
commit186a277e317a14dcba5a2d709f2fbd8c078dfa6f
tree99fadebdcef48833e917488745a41ef7edaf3095
parent62d4a5e149552ef1f1757197652ae7be4fc9f3a3
drm/i915/icl: add the main CDCLK functions

This commit adds the basic CDCLK functions, but it's still missing
pieces of the display initialization sequence.

v2:
 - Implement the voltage levels.
 - Rebase.
v3:
 - Adjust to the new "bypass" clock (Imre).
 - Call intel_dump_cdclk_state() too.
 - Rename a variable to avoid confusion.
 - Simplify the DVFS part.
v4:
 - Remove wrong bit definition (James).
 - Also drive-by fix the coding style for the register definition we
   touched.
v5:
 - Comment style (checkpatch).

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180206193346.18272-1-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_cdclk.c
drivers/gpu/drm/i915/intel_drv.h