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(parent: 65a401f) | patch
[ARM] Fix selection of VLDR.16 instruction with imm offset
authorOliver Stannard <oliver.stannard@arm.com>
Mon, 4 Mar 2019 09:17:38 +0000 (09:17 +0000)
committerOliver Stannard <oliver.stannard@arm.com>
Mon, 4 Mar 2019 09:17:38 +0000 (09:17 +0000)
commit181afc7f3bb965cac3b911ef6c82519876a68e78
tree939b78f330dfea1235ab1713138b6570d37f4959tree | snapshot
parent65a401f6a90f8440fed1bcf89b5c3da4d61538a2commit | diff
[ARM] Fix selection of VLDR.16 instruction with imm offset

The isScaledConstantInRange function takes upper and lower bounds which are
checked after dividing by the scale, so the bounds checks for half, single and
double precision should all be the same. Previously, we had wrong bounds checks
for half precision, so selected an immediate the instructions can't actually
represent.

Differential revision: https://reviews.llvm.org/D58822

llvm-svn: 355305
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/ARM/fp16-load-store.ll [new file with mode: 0644] blob
Domain: System / Toolchain;