MIPS: traps: 64bit kernels should read CP0_EBase 64bit
authorJames Hogan <james.hogan@imgtec.com>
Thu, 1 Sep 2016 16:30:07 +0000 (17:30 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 4 Oct 2016 14:13:57 +0000 (16:13 +0200)
commit18022894eca1315851bfd0614f011fbc01e44d16
treef61b703336511bb9b9f4a469ce85553fedae290c
parent72bc8c75eaf72aa0e45652d09f1b80dd5346797e
MIPS: traps: 64bit kernels should read CP0_EBase 64bit

When reading the CP0_EBase register containing the WG (write gate) bit,
the ebase variable should be set to the full value of the register, i.e.
on a 64-bit kernel the full 64-bit width of the register via
read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
including bits 31:30 which may be writeable.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14148/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/traps.c