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author	Jonas Paulsson <paulsson@linux.vnet.ibm.com>
	Thu, 1 Dec 2022 18:33:11 +0000 (19:33 +0100)
committer	Jonas Paulsson <paulsson@linux.vnet.ibm.com>
	Sat, 3 Dec 2022 20:15:15 +0000 (14:15 -0600)
commit	17db0de330f943833296ae72e26fa988bba39cb3
tree	433e27a59c2c7a331eaf94daa0ff44f0f74ac6a0	tree \| snapshot
parent	9a41739565d9f7ce94da5e7d83947ead73d9bd54	commit \| diff

Reapply "[CodeGen] Add new pass for late cleanup of redundant definitions."

Init captures added in processBlock() to avoid capturing structured bindings,
which caused the build problems (with clang).

RISCV has this disabled for now until problems relating to post RA pseudo
expansions are resolved.

58 files changed:

llvm/include/llvm/CodeGen/CodeGenPassBuilder.h		diff \| blob \| history
llvm/include/llvm/CodeGen/MachinePassRegistry.def		diff \| blob \| history
llvm/include/llvm/CodeGen/Passes.h		diff \| blob \| history
llvm/include/llvm/InitializePasses.h		diff \| blob \| history
llvm/lib/CodeGen/CMakeLists.txt		diff \| blob \| history
llvm/lib/CodeGen/CodeGen.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp	[new file with mode: 0644]	blob
llvm/lib/CodeGen/TargetPassConfig.cpp		diff \| blob \| history
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp		diff \| blob \| history
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp		diff \| blob \| history
llvm/test/CodeGen/AArch64/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cc-update.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/flat-scratch.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/multilevel-break.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/fpclamptosat.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/jump-table-islands.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/reg_sequence.ll		diff \| blob \| history
llvm/test/CodeGen/BPF/objdump_cond_op_2.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/shl.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/cgp-select.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/fast-isel-branch.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/SystemZ/frame-28.mir	[new file with mode: 0644]	blob
llvm/test/CodeGen/Thumb/frame-access.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll		diff \| blob \| history
llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll		diff \| blob \| history
llvm/test/CodeGen/X86/AMX/amx-across-func.ll		diff \| blob \| history
llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fast-isel-stackcheck.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fshl.ll		diff \| blob \| history
llvm/test/CodeGen/X86/masked_load.ll		diff \| blob \| history
llvm/test/CodeGen/X86/oddshuffles.ll		diff \| blob \| history
llvm/test/CodeGen/X86/opt-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/X86/sdiv_fix_sat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shift-i128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/ushl_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_extract.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_shift5.ll		diff \| blob \| history
llvm/test/CodeGen/XCore/scavenging.ll		diff \| blob \| history

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