i2c-designware: always set the STOP bit after last byte
authorMika Westerberg <mika.westerberg@linux.intel.com>
Thu, 17 Jan 2013 10:31:05 +0000 (12:31 +0200)
committerWolfram Sang <w.sang@pengutronix.de>
Mon, 28 Jan 2013 04:26:42 +0000 (05:26 +0100)
commit17a76b4b32aca7c19df6988213dfe2eb4b631431
tree06a41fa292a7af4e8001ee1157bcb9574fd0d932
parent5c38dc8911b86b7c49305e2f2b631cd1241f2d87
i2c-designware: always set the STOP bit after last byte

If IC_EMPTYFIFO_HOLD_MASTER_EN is set to one, the DesignWare I2C controller
doesn't generate STOP on the bus when the FIFO is empty. This violates the
rules of Linux I2C stack as it requires that the STOP is issued once the
i2c_transfer() is finished.

However, there is no way to detect this from the hardware registers, so we
must make sure that the STOP bit is always set once the last byte of the
last message is transferred.

This patch is based on the work of Dirk Brandewie.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
drivers/i2c/busses/i2c-designware-core.c