[DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler.
authorAndrew Ng <anng.sw@gmail.com>
Tue, 25 Apr 2017 13:39:49 +0000 (13:39 +0000)
committerAndrew Ng <anng.sw@gmail.com>
Tue, 25 Apr 2017 13:39:49 +0000 (13:39 +0000)
commit178c369456a5ad187d6a08e3b269a81300825775
tree0af3e4ac0b63ffed902dc381bc81b17f69d6f20f
parent986d73cc1d9528c3ee360cf128c65788035ebdc9
[DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler.

This patch fixes a bug with the updating of DBG_VALUE's in
BreakAntiDependencies. Previously, it would only attempt to update the first
DBG_VALUE following the instruction whose register is being changed,
potentially leaving DBG_VALUE's referring to the wrong register. Now the code
will update all DBG_VALUE's that immediately follow the instruction.

This issue was detected as a result of an optimized codegen difference with
"-g" where an X86 byte/word fixup was not performed due to a DBG_VALUE
referencing the wrong register.

Differential Revision: https://reviews.llvm.org/D31755

llvm-svn: 301309
llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
llvm/lib/CodeGen/AntiDepBreaker.h
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir [new file with mode: 0644]