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(parent: 298beb5) | patch
[mips] Add backend support for Mips32r[35] and Mips64r[35].
authorDaniel Sanders <daniel.sanders@imgtec.com>
Wed, 18 Feb 2015 16:24:50 +0000 (16:24 +0000)
committerDaniel Sanders <daniel.sanders@imgtec.com>
Wed, 18 Feb 2015 16:24:50 +0000 (16:24 +0000)
commit1779314e3c54e6c19dd9df1fabe4b9cf2cb5612e
treeeb72a1ebc9ba0e8d0408b76b86874f22dc31dc81tree | snapshot
parent298beb5e86f6d92638ccb1c5213c59ebd7e45781commit | diff
[mips] Add backend support for Mips32r[35] and Mips64r[35].

Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: tomatabacu, llvm-commits, atanasyan

Differential Revision: http://reviews.llvm.org/D7381

llvm-svn: 229695
62 files changed:
llvm/include/llvm/Support/ELF.h diff | blob | history
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp diff | blob | history
llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h diff | blob | history
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp diff | blob | history
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp diff | blob | history
llvm/lib/Target/Mips/Mips.td diff | blob | history
llvm/lib/Target/Mips/MipsSubtarget.h diff | blob | history
llvm/lib/Target/Mips/MipsTargetStreamer.h diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/add.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/and.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/call.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/mul.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/or.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/ret.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/select.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/shl.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/srem.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/sub.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/urem.ll diff | blob | history
llvm/test/CodeGen/Mips/llvm-ir/xor.ll diff | blob | history
llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-le.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-le.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt diff | blob | history
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt [new file with mode: 0644] blob
llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt [new file with mode: 0644] blob
llvm/test/MC/Mips/elf_eflags.s diff | blob | history
llvm/test/MC/Mips/mips32r3/abiflags.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r3/invalid-mips64r2.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r3/invalid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r3/valid-xfail.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r3/valid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r5/abiflags.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r5/invalid-mips64r2.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r5/invalid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r5/valid-xfail.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips32r5/valid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r3/abi-bad.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r3/abiflags.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r3/invalid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r3/valid-xfail.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r3/valid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r5/abi-bad.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r5/abiflags.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r5/invalid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r5/valid-xfail.s [new file with mode: 0644] blob
llvm/test/MC/Mips/mips64r5/valid.s [new file with mode: 0644] blob
llvm/test/MC/Mips/set-arch.s diff | blob | history
llvm/test/MC/Mips/set-mips-directives-bad.s diff | blob | history
llvm/test/MC/Mips/set-mips-directives.s diff | blob | history
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