drm/i915: Use a hybrid scheme for fast register waits
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 30 Jun 2016 14:32:44 +0000 (15:32 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 30 Jun 2016 14:41:58 +0000 (15:41 +0100)
commit1758b90e38f53b93821c908201826e825a37cb65
tree7b47d24e7690862c514b529fc6e384d4bf76c270
parent527b6abe5fd2d24fba69e9564a2d608e1796ca8d
drm/i915: Use a hybrid scheme for fast register waits

Ville Syrjälä reported that in the majority of wait_for(I915_READ()) he
inspect, most completed within the first couple of reads and that the
delay between those wait_for() reads was the ratelimiting step for many
code paths. For example, __gen6_update_ring_freq() was blamed for
slowing down boot by many milliseconds, but under Ville's scrutiny the
issue was just excessive delay waiting for sandybridge_pcode_write().

We can eliminate the wait by initially using a busyspin upon the register
read and only fallback to the sleeping loop in cases where the hardware
is indeed too slow. A threshold of 2 microseconds is used as the initial
ballpark.

To avoid excessive code bloating from converting every wait_for() into a
hybrid busy/sleep loop, we extend wait_for_register_fw() and export it
for use by other callers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467297225-21379-1-git-send-email-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_uncore.c