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(parent: 18f67c8) | patch
i965/tcs/scalar: only update imm_offset for second message in 64bit input loads
authorIago Toral Quiroga <itoral@igalia.com>
Fri, 15 Jul 2016 08:48:03 +0000 (10:48 +0200)
committerIago Toral Quiroga <itoral@igalia.com>
Mon, 18 Jul 2016 07:53:16 +0000 (09:53 +0200)
commit1737e75bfb85eb22a30e4f1c69a825b3abd946f6
treecc312265de6ceff993a3a6ed1cff430b7b445b76tree | snapshot
parent18f67c8a69fcde5d3f585effeef670d0861b0730commit | diff
i965/tcs/scalar: only update imm_offset for second message in 64bit input loads

Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
src/mesa/drivers/dri/i965/brw_fs_nir.cpp diff | blob | history
Domain: Graphics System / GL;