[RISCV] Manually emit the best shift for VSCALE lowering to improve codegen.

[RISCV] Manually emit the best shift for VSCALE lowering to improve codegen.

We assume VLENB is a multiple of 8 and previously relied on shift
pairs being optimized to an AND+SHL/SHR and computeKnownBits
removing the AND. This doesn't happen if (vlenb >> 3) gets CSEd
to have multiple uses. This patch manually emits the best shift
to workaround this.