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(parent: 1ce552f) | patch
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 8 Oct 2019 17:04:41 +0000 (10:04 -0700)
committerMatt Arsenault <arsenm2@gmail.com>
Fri, 25 Oct 2019 20:11:09 +0000 (13:11 -0700)
commit171cf5302f43776b07615e32b2ffd6ddf4e5d890
tree1f029fd31e417dba705e7fbfd15469fbb8f8a683tree | snapshot
parent1ce552f3ef8d6455c10a9886191c1898594975e0commit | diff
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG

Custom lower this to a target instruction with the merge operands. I
think it might be better to directly select this and emit a
REG_SEQUENCE, but this would be more work since it would require
splitting the tablegen patterns for these cases from the other
atomics.
12 files changed:
llvm/lib/Target/AMDGPU/AMDGPUGISel.td diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPUInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/FLATInstructions.td diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.h diff | blob | history
llvm/lib/Target/AMDGPU/SIInstructions.td diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir diff | blob | history
Domain: System / Toolchain;