drm/i915/dg2: Update steering tables
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 29 Jul 2021 16:59:54 +0000 (09:59 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 5 Aug 2021 15:06:01 +0000 (08:06 -0700)
commit1705f22c86fb2654df22169c020d9d4ff193e47b
tree29b520dc81f0b5537b64135c5d2cf8b0a254fd4d
parent768fe28dd3dcea517d3c491cfe1b5cd768ee1334
drm/i915/dg2: Update steering tables

DG2's replicated register ranges are almost the same at XeHP SDV with
the exception of one LNCF sub-range that switches to gslice steering.
We can re-use the XeHP SDV mslice steering table and just provide a
DG2-specific LNCF steering table.

Bspec: 66534
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729170008.2836648-5-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_gt.c