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(parent: 8d0f567) | patch
agp/intel: fix cache control for sandybridge
authorZhenyu Wang <zhenyuw@linux.intel.com>
Tue, 2 Nov 2010 09:30:46 +0000 (17:30 +0800)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 4 Nov 2010 09:39:50 +0000 (09:39 +0000)
commit16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c
tree8a4d083794272b7d7bf82aad75076a7722164b23tree | snapshot
parent8d0f56708292ca5c256ee3b7187d124afee81d93commit | diff
agp/intel: fix cache control for sandybridge

This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/char/agp/intel-gtt.c diff | blob | history
Domain: SCM / Uncategorized;