[AMDGPU] Make some VOP3 insts commutable
authorJoe Nash <Joseph.Nash@amd.com>
Mon, 29 Mar 2021 18:58:29 +0000 (14:58 -0400)
committerJoe Nash <Joseph.Nash@amd.com>
Wed, 28 Apr 2021 17:59:08 +0000 (13:59 -0400)
commit168228d76a1c0e1003bccc213d1db9d8ff9f5ac9
treec995252ca595bda603485b8c459fce20dc3c4334
parentfa0d044c4499535fb7960a5b7053bd043ad09e52
[AMDGPU] Make some VOP3 insts commutable

Note, only src0 and src1 will be commuted if the isCommutable flag
is set. This patch does not change that, it just makes it possible
to commute src0 and src1 of some U/I/B vop3 instructions.

This patch revises d35d8da7d6ac6c08578ec0569b072292631691e0.
It contains the commute opportunities excluding float insts

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D101474

Change-Id: I62938173d750453839f2457a3851661a29135faf
13 files changed:
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll
llvm/test/CodeGen/AMDGPU/commute-vop3.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll