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(parent: c8ba52d) | patch
MIPS: mm: XBurst CPU requires sync after DMA
authorPaul Cercueil <paul@crapouillou.net>
Sun, 30 May 2021 17:17:55 +0000 (18:17 +0100)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Tue, 1 Jun 2021 09:44:46 +0000 (11:44 +0200)
commit1660710cf5d8d44ec351a5df57c35516f1fbf5e0
tree591624fadbf915c66cef78f5afc7d5c35ae4833ctree | snapshot
parentc8ba52d1b7e317c54d461970e4bdeec10ea1d9c4commit | diff
MIPS: mm: XBurst CPU requires sync after DMA

I am not sure why this is required, but if this is not enabled, reading
from a buffer in which data has been DMA'd may read incorrect values.

This used to happen for instance in mmc_app_send_scr()
(drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied
by the CPU to a different location.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/Kconfig diff | blob | history
arch/mips/mm/dma-noncoherent.c diff | blob | history
Domain: System / Kernel;