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[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the...
authorCraig Topper <craig.topper@sifive.com>
Thu, 15 Apr 2021 18:08:26 +0000 (11:08 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 15 Apr 2021 18:08:28 +0000 (11:08 -0700)
commit1656df13daa146afeb75ad832c94830a1f47d9cf
tree9eca5f9be667166e294148258172397d044ac65etree | snapshot
parente0c2125d1d1e72039b8e071d468d9f740c7dbfbdcommit | diff
[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension.

This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100424
llvm/lib/Target/RISCV/RISCVInstrFormats.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoB.td diff | blob | history
Domain: System / Toolchain;