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[RISCV] Add inline asm constraint A for RISC-V
authorLewis Revill <lewis.revill@embecosm.com>
Fri, 16 Aug 2019 10:23:56 +0000 (10:23 +0000)
committerLewis Revill <lewis.revill@embecosm.com>
Fri, 16 Aug 2019 10:23:56 +0000 (10:23 +0000)
commit1653ebee3f04f0591a0f31017cdd5059828ef6e5
treeb777ed4c3460678ed2e281150dcc331ce10bd2e8tree | snapshot
parent8b593480d33f8e8f5c4ec1f921a2c692bd0b7f45commit | diff
[RISCV] Add inline asm constraint A for RISC-V

This allows the constraint A to be used in inline asm for RISC-V, which
allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

Differential Revision: https://reviews.llvm.org/D54295

llvm-svn: 369093
clang/lib/Basic/Targets/RISCV.cpp diff | blob | history
clang/test/CodeGen/riscv-inline-asm.c diff | blob | history
Domain: System / Toolchain;