drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
authorManasi Navare <manasi.d.navare@intel.com>
Fri, 22 Jan 2021 23:26:42 +0000 (15:26 -0800)
committerManasi Navare <manasi.d.navare@intel.com>
Mon, 25 Jan 2021 23:23:18 +0000 (15:23 -0800)
commit1639406a31c23ca07a2b8a9b45d1c400debda9e9
tree8c841e25cdc6659fe5989d2f7d5af5f4339079c5
parentf065123299f5af97e9a41567560413d453279d5e
drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink

If VRR is enabled, the sink should ignore MSA parameters
and regenerate incoming video stream without depending
on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN
bit if VRR is enabled.
Reset this bit on VRR disable.

v2:
* ACtually set the dpcd msa ignore bit (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c
drivers/gpu/drm/i915/display/intel_dp_link_training.c