[InstCombine] reassociate bitwise logic chains based on uses
authorSanjay Patel <spatel@rotateright.com>
Sun, 21 Aug 2022 13:42:14 +0000 (09:42 -0400)
committerSanjay Patel <spatel@rotateright.com>
Sun, 21 Aug 2022 13:42:14 +0000 (09:42 -0400)
commit15e3d869119289991072679f82622072818468e6
tree9159000ff54bc0d3b49123b74ac1422042fa672a
parent952f90b72b3546d6b6b038d410f07ce520c59b48
[InstCombine] reassociate bitwise logic chains based on uses

(X op Y) op Z --> (Y op Z) op X

This isn't a complete solution (see TODO tests for possible refinements),
but it shows some nice wins and doesn't seem to cause any harm. I think
the most potential danger is from conflicting with other folds and causing
an infinite loop - that's the reason for avoiding patterns with constant
operands.

Alternatively, we could try this in the reassociate pass, but we would not
immediately see all of the logic folds that instcombine provides. I also
looked at improving ValueTracking's isImpliedCondition() (and we should
still add some enhancements there), but that would not work in general for
bitwise logic reduction.

The tests that reduce completely to 0/-1 are motivated by issue #56653.

Differential Revision: https://reviews.llvm.org/D131356
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
llvm/test/Transforms/InstCombine/and-or-icmps.ll
llvm/test/Transforms/InstCombine/and-or-not.ll
llvm/test/Transforms/InstCombine/and-or.ll
llvm/test/Transforms/InstCombine/and-xor-or.ll
llvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
llvm/test/Transforms/LoopVectorize/reduction-predselect.ll