x86: fix handling of 64-bit operand size VPCMPESTR{I,M}
authorJan Beulich <jbeulich@novell.com>
Tue, 28 Feb 2017 09:53:35 +0000 (10:53 +0100)
committerJan Beulich <jbeulich@suse.com>
Tue, 28 Feb 2017 09:53:35 +0000 (10:53 +0100)
commit15c7c1d8a535000e94ed36f4259d0ede32001408
treef7cb2504df939990ac7118de6862d57590ca591c
parent4ef97a1b459849ad190244c36b36d45bdd078030
x86: fix handling of 64-bit operand size VPCMPESTR{I,M}

Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.

Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.

Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
18 files changed:
gas/ChangeLog
gas/testsuite/gas/i386/ilp32/x86-64-avx-intel.d
gas/testsuite/gas/i386/ilp32/x86-64-avx.d
gas/testsuite/gas/i386/ilp32/x86-64-sse2avx.d
gas/testsuite/gas/i386/ilp32/x86-64-sse4_2-intel.d
gas/testsuite/gas/i386/ilp32/x86-64-sse4_2.d
gas/testsuite/gas/i386/x86-64-avx-intel.d
gas/testsuite/gas/i386/x86-64-avx.d
gas/testsuite/gas/i386/x86-64-avx.s
gas/testsuite/gas/i386/x86-64-sse2avx.d
gas/testsuite/gas/i386/x86-64-sse2avx.s
gas/testsuite/gas/i386/x86-64-sse4_2-intel.d
gas/testsuite/gas/i386/x86-64-sse4_2.d
gas/testsuite/gas/i386/x86-64-sse4_2.s
opcodes/ChangeLog
opcodes/i386-dis.c
opcodes/i386-opc.tbl
opcodes/i386-tbl.h