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(parent: 11bd958) | patch
[InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IR
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 27 Jul 2015 18:52:15 +0000 (18:52 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 27 Jul 2015 18:52:15 +0000 (18:52 +0000)
commit15c0a5946314ed8000becbbb0d13e6429759f202
treec5e88b1baa22305b7143df96bd3da3bf72843231tree | snapshot
parent11bd958cb673b1af9892ed820087b8a4cc62a480commit | diff
[InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IR

Now that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code.

Differential Revision: http://reviews.llvm.org/D11503

llvm-svn: 243303
llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp diff | blob | history
llvm/test/Transforms/InstCombine/vec_demanded_elts.ll diff | blob | history
llvm/test/Transforms/InstCombine/x86-pmovsx.ll [new file with mode: 0644] blob
llvm/test/Transforms/InstCombine/x86-pmovzx.ll [new file with mode: 0644] blob
Domain: System / Toolchain;