projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8c47103) | patch
[AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.
authorJun Ma <JunMa@linux.alibaba.com>
Wed, 25 Aug 2021 11:25:38 +0000 (19:25 +0800)
committerJun Ma <JunMa@linux.alibaba.com>
Fri, 27 Aug 2021 12:03:48 +0000 (20:03 +0800)
commit15b2a8e7faf6b10c1371d0283a0287cf2c93ed0e
tree13e34c636818ee26c87f28a526100fd6510c7a16tree | snapshot
parent8c471034919702d83c59759bbf4c3a606ac1fab4commit | diff
[AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

For vectors that are exactly equal to getMaxSVEVectorSizeInBits, just use
AArch64SVEPredPattern::all, which can enable the use of unpredicated ptrue when available.

TestPlan: check-llvm

Differential Revision: https://reviews.llvm.org/D108706
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll diff | blob | history
llvm/test/CodeGen/AArch64/sve-extract-vector.ll diff | blob | history
llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/sve-insert-vector.ll diff | blob | history
llvm/test/CodeGen/AArch64/sve-vscale-attr.ll diff | blob | history
Domain: System / Toolchain;