[X86][AVX] LowerBUILD_VECTOR - reduce 256/512-bit build vectors with zero/undef upper...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 14 Dec 2020 17:49:33 +0000 (17:49 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 15 Dec 2020 10:11:38 +0000 (10:11 +0000)
commit15a31389b2ead8fa7052a4378b76b5d686d29ad7
treef477bfcd1cd67bb2e5c87a400e808a0ebc4d5e85
parent8a7e770638f00c5c8657044b44ca34f471d29511
[X86][AVX] LowerBUILD_VECTOR - reduce 256/512-bit build vectors with zero/undef upper elements + pad.

As discussed on D92645, we don't do a good job of recognising when we don't require the full width of a ymm/zmm build vector because the upper elements are undef/zero.

This commit allows us to make use of implicit zeroing of upper elements with AVX instructions, which we emulate in DAG with a INSERT_SUBVECTOR into the bottom of a undef/zero vector of the original type.

This exposed a limitation in getTargetConstantBitsFromNode which didn't extract bits from INSERT_SUBVECTORs of different element widths which I've included as well to prevent a couple of regressions.
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
llvm/test/CodeGen/X86/pr29112.ll
llvm/test/CodeGen/X86/pr46532.ll
llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
llvm/test/CodeGen/X86/trunc-subvector.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll