projects / platform / kernel / linux-rpi.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0ab55cf) | patch
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 30 Apr 2022 11:41:48 +0000 (12:41 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:20 +0000 (12:10 +0200)
commit1561380ee72f55e3a86856ee046532c18d3e9855
treeab72974348d7530f90d9c7aa4adf23a81d5657a6tree | snapshot
parent0ab55cf1834177a2162757fee2ac3cb6730beb20commit | diff
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support

PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.

This patch adds support for generating FOUTPOSTDIV clk.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/rzg2l-cpg.c diff | blob | history
drivers/clk/renesas/rzg2l-cpg.h diff | blob | history
Domain: System / Kernel;