[llvm][sve] Lowering for VLS truncating stores
authorDavid Truby <david.truby@arm.com>
Mon, 12 Jul 2021 09:55:11 +0000 (10:55 +0100)
committerDavid Truby <david.truby@arm.com>
Fri, 23 Jul 2021 13:04:55 +0000 (14:04 +0100)
commit1528a4d40022925dcc3e8cb6b8af7dd109ad7075
tree9761728230a45c6ac8810b6511da5b44817216af
parentf97de4cb0be43730bd91b800fa7f5418364ba3fd
[llvm][sve] Lowering for VLS truncating stores

This adds custom lowering for truncating stores when operating on
fixed length vectors in SVE. It also includes a DAG combine to
fold extends followed by truncating stores into non-truncating
stores in order to prevent this pattern appearing once truncating
stores are supported.

Currently truncating stores are not used in certain cases where
the size of the vector is larger than the target vector width.

Differential Revision: https://reviews.llvm.org/D104471
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AMDGPU/R600ISelLowering.h
llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll [new file with mode: 0644]
llvm/test/CodeGen/Mips/cconv/byval.ll
llvm/test/CodeGen/Mips/cconv/vector.ll
llvm/test/CodeGen/Mips/llvm-ir/store.ll