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(parent: 1ac36b3) | patch
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns
authorFraser Cormack <fraser@codeplay.com>
Mon, 11 Jan 2021 17:42:05 +0000 (17:42 +0000)
committerFraser Cormack <fraser@codeplay.com>
Mon, 25 Jan 2021 22:03:52 +0000 (22:03 +0000)
commit15141cd115e068104cc61f32ada05bebf5ef03a5
tree6038d4d0667541090d4539e28eef586aa6d8ab9atree | snapshot
parent1ac36b34db81d2fccd2b4a98d497be62083de3b1commit | diff
[RISCV] Add RVV insertelt/extractelt scalable-vector patterns

Original patch by @rogfer01.

This patch adds support for insertelt and extractelt operations on
scalable vectors.

Special care must be taken on RV32 when dealing with i64 vectors as
there are no straightforward ways to insert a 64-bit element without a
register of that size. To that end, both are custom-lowered to different
sequences.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Fraser Cormack <fraser@codeplay.com>
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94615
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.h diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td diff | blob | history
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll [new file with mode: 0644] blob
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