cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
authorDan Williams <dan.j.williams@intel.com>
Wed, 18 May 2022 23:34:48 +0000 (16:34 -0700)
committerDan Williams <dan.j.williams@intel.com>
Thu, 19 May 2022 15:50:41 +0000 (08:50 -0700)
commit14d78874077442d1d0f08129f5a0ea5070984b4b
tree4c80ac1f7f8fb934b3a430fdcdacee9d40e47f05
parent2e4ba0ec978335b4b550bbed95cb198ac3a00745
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core

In preparation for fixing the setting of the 'mem_enabled' bit in CXL
DVSEC Control register, move all CXL DVSEC range enumeration into the
same source file.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291688886.1426646.15046138604010482084.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
drivers/cxl/core/pci.c
drivers/cxl/cxlmem.h
drivers/cxl/cxlpci.h
drivers/cxl/mem.c
drivers/cxl/pci.c
tools/testing/cxl/Kbuild
tools/testing/cxl/test/mem.c
tools/testing/cxl/test/mock.c