gfx: drv: cleanup dsi pll lock loop in mdfld_restore_display_registers

gfx: drv: cleanup dsi pll lock loop in mdfld_restore_display_registers

Use the already existing macro to wait for the HW flag becoming set. The
current timeout value will change from the current 3 second. The actual
PLL settling time according to measurement is < 100usec or 200
iterations of the busy wait loop. So the new timeout duration of 100000
iterations should be enough.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>