rs6000: Optimize __builtin_shuffle when it's used to zero the upper bits [PR102868]

rs6000: Optimize __builtin_shuffle when it's used to zero the upper bits [PR102868]

If the second operand of __builtin_shuffle is const vector 0, and with
specific mask, it can be optimized to vspltisw+xxpermdi instead of lxv.

gcc/ChangeLog:

	PR target/102868
	* config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Add
	patterns match and emit for VSX xxpermdi.

gcc/testsuite/ChangeLog:

	PR target/102868
	* gcc.target/powerpc/pr102868.c: New test.